The present invention generally relates to a method for manufacturing a semiconductor device. The semiconductor device is included in various apparatuses, such as a mobile phone and a computer. More particularly, the present invention relates to a method for manufacturing a semiconductor package, such as a ball grid array (BGA) package, comprising a semiconductor chip having a center pad structure. The semiconductor chip having the center pad structure comprises a principal surface and a line of pads provided with a plurality of pads arranged on a center region of the principal surface.
The BGA package comprises a semiconductor chip, such as a DRAM chip, having the center pad structure. The BGA package further comprises an insulator tape and a plurality of solder balls. The insulator tape has an upper surface and a lower surface. The semiconductor chip is mounted on the upper surface of the insulator tape. Between the insulator tape and the semiconductor chip, an elastomer layer is present. The plurality of solder balls as external terminals are arranged on the lower surface. For example, known techniques are disclosed in JP-A 2001-274323 and JP-A H11-87409, which are incorporated herein by reference in their entireties.
An arrangement of the plurality of solder balls in the BGA package is standardized by JEDEC for achieving greater versatility.
The BGA package further comprises a plurality of DQ lines, a plurality of VDDQ lines and a plurality of VSSQ lines. To improve the data transfer rate of the DRAM, one of the DQ lines should be arranged between one of the VDDQ lines related to the one of the DQ line and one of the VSSQ lines related to the one of the DQ line so that the plurality of DQ lines are shielded each other. The arrangement also causes feedback current illustrated in FIG. 1 relating to both logical low output and logical high output to flow through a nearest VDDQ line and a nearest VSSQ line so that the effective inductance for signals relating to the plurality of DQ lines is lowered.
Because the number of pads on the DRAM chip are limited and a layout of lines in the BGA package has constraint. Some of the DQ lines are not arranged between the VDDQ lines and the VSSQ lines according to the known techniques.
Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device having a layout in which a signal line, such as a DQ line, arranged between a power line relating to the signal line, such as a VDDQ line, and a ground line relating to the signal line, such as a VSSQ line. The power line relating to the signal line and the ground line relating to the signal line are different from a power line and a ground line of the semiconductor chip. Moreover, it is further object of the present invention to provide the semiconductor device and an apparatus comprising the same.